Thangadurai Arivoli

Digital Engineer

Contact

Wireless Technologies Laboratory
CSIRO ICT Centre
PO Box 76
Epping NSW 1710

Mob: 0432 568 485
Email

Projects

• Adaptive Wireless

Science Area

• Communications and Signal Processing

Biography

EXPERIENCE: 12 years of ASIC design – (total of 20 years)

In the recent past, I have worked mainly in ASIC design (product), IP development in Wireless/DSP domains.

I have contributed to 6 tape-outs, which include the following.
• LowPower Mixed signal DSP (0.13u NEC)
• RM11a (the award winning IEEE STD 802.11a PHY compliant chip – 0.25u TSMC)
• DMT50 (Discrete Multi Tone modem – 0.6u MOSIS)
• 16-point FFT (0.6u MOSIS)

The following IPs have been developed.
• 802.11i complaint encryption/decryption core design
• 802.15.3 WPAN Baseband Processor

SUMMARY:
• Thorough knowledge of the ASIC design flow. Experience in various methodologies.
• Sound knowledge in the field of Physics of Semiconductor Devices.

ASIC design: Experienced in front-end and back-end design. Logic design has been done using verilog. Verilog-XL and ModelSim have been used extensively. Cadence tool suite has been used for back-end. Exposure to Magma's physical synthesis. Involved in ATE testing.

FPGA design: Implementation of complex designs in Xilinx chips (XC3020 to Virtex1000). Schematics and Verilog based design entry have been used.

PCB design: High Speed board design using Protel

Component Engineering:
• Q & R evaluation tests for ICs
• Vendor qualification for PCBs
• Failure Analysis of ICs – basic.

EDA TOOLS USED:
• Front end - Model sim, Verilog-XL, Magma physical synthesis
• Back end - Cell3 Ensemble (P&R)
- Pearl (post routed timing analysis), ATPG(TetraMax), ATE testing

TRAINING:
• Quality and Reliability of Electronic Components
• Failure Analysis of Electronic Components including ICs
• SMT soldering

Academic Qualifications

1986	PhD Indian Institute of Science, India
1982	M.Sc(Eng) Indian Institute of Science, India
1978	M.Sc The American College, Tamil Nadu, India

Recent Professional Experience

2006	Digital Engineer, ICT Centre, CSIRO. Development of MIMO Wireless system for data rate ~600 Mbps. SISO Modelling using Simulink and "Xilinx's system generator has been completed. The design has been synthesized and been tested with the existing xilinx & RF Platform.
2003	Technical Lead, Nulife Semiconductor Pvt Ltd. Chennai. Digital design for Low Power (~1mW) Mixed signal DSP for Hearing Aid application. Responsible for Datapath design, Top level digital integration of the DSP and Test vector generation for ATE
2002	Member Technical Staff, Avedis Micro systems, Bangalore. Involved in the IP development - WPAN (802.15.3), Encryption / Decryption core (802.11i)
2001	Consultant, Sasken Communication Technologies Ltd, Bangalore
1999	Principal Engineer, Radiata Communications Pty. Ltd. Australia. ASIC Design: IEEE STD 802.11a PHY compliant chip (RM11a) - Logic design using verilog. Assisting to implement the design in Virtex1000. Post-layout timing analysis using Pearl
1994	Project Engineer, Macquarie University, Australia. ASIC Design: Complete Design (Front-end and Back-end) of OFDM Modem chip (DMT50) and 16-point FFT with cyclic extension (Logic design using verilog, P&R using Cadence’s Cell3 Ensemble and Post-layout timing analysis using Pearl). Board design using Protel

Summary of Science & Technical Output

Top 10 Publications

Publication details
Philip Ryan, Thangadurai Arivoli, Ludovico de Souza, Gordon Foyster, Richard Keaney, Tom McDermott, Alireza Moini, Said Al-Sarawi, Uri Parker, Geoff Smith, Neil Weste, Greg Zyner, “A Single Chip PHY COFDM Modem for IEEE 802.11a with Integrated ADCs and DA
T. Arivoli, M.Bickerstaff, P.J. Ryan, T.McDermott, N.Weste, D.J. Skellern, and T.M. Percival, “A Single Chip DMT Modem for High-Speed WLANs”, Proceedings of CICC’98, 1998
M.Bickerstaff, P.J. Ryan, T. Arivoli, N.Weste, D.J. Skellern, “A Low Power 50MHz FFT Processor with Cyclic Extension and Shaping Filter” Proceedings of the ASP-DAC’98
N.Weste, M.Bickerstaff, T. Arivoli, P.J. Ryan, J.Dalton, D.J. Skellern, and T.M. Percival, “A 50MHz 16-point FFT Processor for WLAN Applications”, IEEE Custom Integrated Circuits Conference, 1997
N. Weste, G.Foyster, M.Bickerstaff, T. Arivoli, T.McDermott, “MacFLOW - A CMOS technology independent HDL design flow” Proceedings of the IREE Society ’97
N. Weste, M.Bickerstaff, T. Arivoli, P. Ryan, D.J. Skellern, T. Percival, “A Low Power 50MHz FFT Processor with Cyclic Extension and Shaping Filter” Proceedings of the IREE Society ’97
J. Steel, J. Haddy, D. Skellern, M. Batty, T. Arivoli, “Digital Transmission Via a Standard Video Channel” 1st Workshop on Applications of Radio Science, WARS ’95 Canberra, ACT, Australia
J. Steel, J. Haddy, D. Skellern, M. Batty, T. Arivoli, “Video Data Networks” Australian Telecommunication Networks and Applications Conference, ATNAC ’95,Sydney, NSW, Australia
T. Arivoli, K. Ramkumar, and M. Satyam, “Magneto resistors based on magnetic composite materials”, Journal of Physics - D: Applied Physics 21 (1988) 636 – 640
T. Arivoli, K. Ramkumar, and M. Satyam, “Magneto resistors based on composites”, Journal of Physics - D: Applied Physics 19 (1986) L183 – L185

Number of citations